The present invention relates generally to integrated circuit write enable signal generating circuitry and methods for driving storage cells which we have found have a tendency to operate improperly if internal feedback in the storage cell turns off for an excessively long period. The invention relates more particularly to driving such cells with a write enable signal having a predetermined level which disables the cell feedback for no longer than a predetermined interval, even though the integrated circuit responds to differing clock frequencies.
FIG. 1 is a block diagram of a prior art programmable integrated circuit register including N identical storage cells 0, 1 . . . 1 . . . (Nxe2x88x921), responsive to clock source 12 having approximately a 50% duty cycle. Clock source 12 drives cells 0, 1 . . . i . . . (Nxe2x88x921) in parallel directly and via inverting driver 10. Cells 0, 1 . . . i . . . (Nxe2x88x921) are also respectively responsive to binary output bits 0, 1 . . . i . . . (Nxe2x88x921) of input signal source 14, write decode source 16 and read decode source 18. A write operation of the bit from source 14 for a particular cell i occurs when write decode source 16 supplies a binary 1 to cell i during the low (ground voltage) half cycle of the inverted clock output of driver 10. The write decode has a positive going transition that initiates the write operation about 100 ps after a positive going transition of clock source 12, for an exemplary 1 GHz clock source. Sources 12 and 16 are synchronized to achieve this result so negative going transitions thereof occur simultaneously. A read operation of the bit which is stored in cell i occurs when read decode source 18 supplies a binary 1 to cell i during the low voltage half cycles of the output of clock source 12 so the read and write operations cannot occur at the same time.
The circuit of cell i, schematically illustrated in FIG. 2, includes a storage cell comprising two back-to-back, regeneratively connected inverters 20 and 22 which selectively have bit i of source 14 written into them. Each of inverters 20 and 22 includes a pair of complementary metal oxide semiconductor (CMOS) field effect transistors (FET) having series connected source drain paths. Inverter 20 is enabled only during the positive half cycle of the output of driver 10 while inverter 22 is enabled whenever the DC power supply terminals 28 and 30 are connected to +VDD and ground. Thereby, bit i from source 14 is stored in cell i at least during the positive voltage half cycles of the output of driver 10. During the low voltage half cycles of the output of driver 10, inverter 20 is disabled and bit i from source 14 can be written into cell i. Such writing occurs if bit i from write decode source 16 has a binary one (positive voltage) value.
To these ends, inverter 20 includes P channel FET 24 and N channel FET 26, having source drain paths connected in series with each other. FETs 24 and 26 are selectively connected between +VDD power supply terminal or rail 28 and ground terminal or rail 30 via the source drain path of N-channel FET 32, having a gate electrode tied to the output of driver 10. FETs 24 and 26 have gate electrodes tied to each other and the output of inverter 22. FETs 24 and 26 have drains tied to each other to form output terminal 33 of inverter 20 which drives the input of inverter 22. Terminal 33 can be considered the storage node of cell i.
Inverter 22 has the same configuration as inverter 20, thus includes complementary FETs 34 and 36. The gate electrodes of FETs 34 and 36 are connected to be driven in parallel by the voltage at terminal 33. The drains of FETs are connected to each other and the gate electrodes of FETs 24 and 26. Terminal 33 is selectively coupled to bit i of input signal source 14 via the source drain path of N-channel FET 38, having a gate electrode responsive to bit i of write decode source 16.
During the half cycle of source 12 while the output of driver 10 is positive, the source drain path of FET 32 is ON, i.e., has a low impedance, to enable inverter 20 so cell i operates in a storage mode. Cell i operates in the storage mode because of the regenerative, positive feedback arrangement of inverters 20 and 22.
To consider the operation of the cell of FIG. 2 during a write operation, i.e., while driver 10 applies a low voltage to FET 32 to disable inverter 20, assume that source 16 has a positive value to turn on FET 38 while source 14 has a positive value. Thereby, cell i stores a binary one voltage substantially equal to +VDD at terminal 33. The high voltage remains at terminal 33 after source 16 turns off FET 38. Similarly, cell i and terminal 33 are at a low substantially ground voltage in response to bit i having a low voltage value while source 16 turns on FET 38. The voltage at terminal 33 remains low after source 16 turns off FET 38. Hence, during the interval while the output of driver 10 is low to turn off FET 32 and disable inverter 20, the voltage at terminal 33 follows the voltage coupled through the source drain path of FET 38.
In response to bit i of write decode source 16 turning on FET 38, which can occur only while FET 32 is off, the voltage at terminal 33 is substantially equal to the voltage bit i of signal source 14 supplies to the source of FET 38. Because FET 32 turns on simultaneously with FET 38 turning off, cell i stores the value of bit i that source 14 supplied to the cell during the write operation.
If bit i of source 14 supplies a positive voltage, representing a binary one, to terminal 33 cell i stores the binary one even when inverter 20 is disabled by the low voltage output of driver 10. This is because the positive voltage at terminal 33 turns on FET 36 and turns off FET 34 to drive FETs 34 and 36 substantially to ground. The ground voltage at the drains of FETs 34 and 36 turns on FET 24, causing +VDD at terminal 28 to be regeneratively supplied to terminal 33.
Writing a zero voltage to terminal 33 does not have a complementary effect because the resulting high voltage at the drains of FETs 34 and 36 turns off FET 24 and turns on FET 26. Since FET 32 is turned off, the drains of FETs 24 and 26 float except for the connection thereof to terminal 33. Hence, if bit i of write decode source 16 is zero when the output of driver 10 is low, the voltage at terminal 33 floats and is influenced significantly by stray charge coupled to terminal 33.
Cell i stores a bit which is read during the half cycle of clock 12 while the output of clock source 12 has a low (i.e., ground) voltage, provided bit i of read decode source 18 has a high value. Thus cell i can be read only while the cell is in the storage mode and cannot be read while the cell is in the write mode. The read circuitry of cell i includes N-channel FETs 40 and 42, and P-channel FET 44. FETs 40-44 have source drain paths series connected between +VDD and ground DC power supply terminals 28 and 30. FETs 40, 42 and 44 have gate electrodes respectively tied to (1) terminal 33, (2) the lead for output bit i of read decode source 18 and (3) the output terminal of clock source 12. The read output terminal 46 of cell i is the common terminal for the drains of complementary transistors 42 and 44.
During a read operation of cell i, the voltage at terminal 46 is the complement of the voltage at terminal 33 because FET 44, when turned on, has a considerably higher source drain impedance than the combined source drain impedance of FETs 40 and 42, when FETs 40 and 42 are turned on. Hence, if the voltage at terminal 33 is high while the low and high outputs of clock source 12 and bit i of source 18 respectively turn on FETs 44 and 42, terminal 46 is pulled down close to the ground potential at terminal 30. If the voltage at terminal 33 is low while clock source 12 and bit i of source 18 are respectively low and high, the high source drain impedance of FET 40 enables the lower source drain impedance of FET 44 to supply the +VDD voltage at terminal 28 to terminal 46.
The cell of FIG. 2 is designed to operate for the normal operating frequency of clock source 12. Thus, FET 32 is designed so it has a metal oxide layer which accumulates a sufficient amount of charge during a small fraction of a low voltage half cycle of source 12 to cause the source drain path of FET 32 to turn on and stay on throughout the low voltage half cycle of source 12. We have found that FET 32 can be designed to perform this function admirably for normal operating frequencies, e.g., 1 GHz, of clock source 12.
However, when the frequency of clock 12 is reduced substantially, e.g., from a normal operating frequency of 1 GHz to a test or sleep frequency of 100 MHz for the integrated circuit including the circuits of FIG. 1, cells of the type illustrated in FIG. 2 have a tendency to malfunction. We have determined that this tendency to malfunction occurs because the charge from the positive input voltage of signal source 14 can accumulate on node 33 even though the source drain path of FET 38 is in a high impedance mode. Since the circuit must operate through a wide range of clock frequencies, it is possible for charge to accumulate on node 33 when the source drain path of FET 32 is in a high impedance mode for a much longer time than in a normal operating mode at 1 GHz. When driver 10 has a low output voltage caused by clock source 12 having a high positive value for an excessive amount of time associated with half cycles of clock 12 that are considerably longer than a 1 GHz half cycle, the high impedance mode of FET 38 and the desired ground voltage on node 33 cannot be restored because of the accumulated charge. Thus, a zero binary value which should be on node 33 is likely to be inadvertently lost, resulting in improper circuit operation and an increase in the probability of cell failure to an unacceptable level.
It is accordingly an object of the invention to provide a new and improved method of and apparatus for driving CMOS integrated circuit storage cells at multiple, significantly different frequencies.
Another object of the invention is to provide a new and improved method of and apparatus for driving CMOS integrated circuit storage cells at multiple, significantly different frequencies, wherein a tendency of the prior art for leakage current to accumulate charge on a node of the cell during low frequency operation is overcome.
An additional object of the invention is to provide a new and improved method of and apparatus for driving CMOS integrated circuit storage cells at multiple, significantly different frequencies, wherein a tendency of the prior art to operate improperly as a result of the circuitry being driven at clock frequencies substantially lower than normal clock frequency operation is overcome.
In accordance with one aspect of the invention, an integrated circuit chip adapted to be responsive to a source of clock waves having differing frequencies at different times includes a bi-level write enable source that drives a write enable input terminal of a memory cell. The cell has a tendency to operate improperly in response to the write enable source deriving the first level for an excessively long duration. The write enable signal source is constructed to respond to the clock waves so that (a) for first clock waves having half cycles of duration less than a predetermined duration the write enable source derives the first level for durations approximately equal to the durations of the half cycles of the first clock waves and (b) for second clock waves having half cycles of duration greater than the predetermined duration the write enable source derives the first level for durations substantially equal to the predetermined duration. The predetermined duration is less than the excessively long duration.
The cell typically includes first and second inverters connected to each other in a back-to-back regenerative circuit so a storage node is between the first and second inverters. A gate electrode of a FET is responsive to the write enable source. The FET is connected to the first inverter to respectively enable and disable the first inverter in response to the write enable source deriving the first level and a second level. The field effect transistor is coupled with the storage node. Charge has a tendency to accumulate on storage node in response to the first level turning off the FET for a duration about equal to the excessively long duration. The storage node has a tendency to respond to the excessive charge to erroneously change the state of a binary signal voltage stored by the cell. Because the write enable signal has a duration less than the excessively long duration even though half cycles of the clock exceed the excessively long duration, excessive charge is not leaked to the node and the stored binary signal voltage does not erroneously change.
In a preferred embodiment, the write enable source includes a timing circuit having a resistance capacitance time constant and inputs responsive to a replica of the clock waves and the write enable source. Preferably, the timing circuit includes first and second complementary field effect transistors having series connected source drain paths. The first field effect transistor is connected to be responsive to the clock waves so that during a first half cycle of each of the clock waves the first field effect transistor supplies current from a DC power supply terminal to a resistance and capacitance in a time constant circuit. During a second half cycle of each of the clock waves the capacitance is decoupled from the DC power supply terminal. The second field effect transistor is connected to be responsive to the write enable source so that (a) during an initial portion of the second half cycles the second field effect transistor discharges the capacitance at a rate determined by the resistance capacitance time constant and (b) during the second half cycles having durations in excess of the predetermined duration the capacitance remains discharged sufficiently to cause the write enable signal to have the second level.
In the preferred embodiment, the timing circuit includes a logic gate having first input responsive to a replica of the clock wave and a second input responsive to a bi-level signal indicative of the voltage across the capacitance. The logic gate is arranged so that (a) during the clock first half cycles the voltage across the capacitance and the clock waves causes the write enable signal to be at the second level, (b) during an initial portion of the second half cycles, (prior to elapse of the predetermined duration) the voltage across the capacitance and the clock wave cause the write enable signal to be at the first level, and (c) after the second half cycle has elapsed for a time substantially equal to or greater than the predetermined duration the voltage across the capacitance has decreased sufficiently to prevent the gate from passing the clock wave to cause the write enable signal to be at the second level.
A further aspect of the invention relates to a method of operating a cell of a semiconductor memory. The cell of the semiconductor memory operates correctly in response to bi-level write enable signals having a first level with durations less than a predetermined value. The cell has a tendency to operate incorrectly in response to the first level of the write enable signals having durations greater than the predetermined value. The method includes deriving clock waves having half cycles less than the predetermined period during a first interval. During the first interval, the first level of the write enable input signal supplied to the memory cell has durations substantially equal to the period of a half cycle of the clock wave. During a second interval the clock wave has half cycles with durations in excess of the predetermined duration. During the second interval, the first level of the write enable input signal supplied to the memory cell has durations no greater than the predetermined duration.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of one specific embodiment thereof, especially when taken in conjunction with the accompanying drawing.